A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g., comprising part of, one, or several dies) on a substrate (e.g., a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
Whichever type of apparatus is employed, the accurate placement of patterns on the substrate is a chief challenge for reducing the size of circuit components and other products that may be produced by lithography. In particular, the challenge of measuring accurately the features on a substrate which have already been laid down is a critical step in being able to position successive layers of features in superposition accurately enough to produce working devices with a high yield. So-called overlay should, in general, be achieved within a few tens of nanometers in today's sub-micron semiconductor devices, down to a few nanometers in the most critical layers.
Consequently, modern lithography apparatuses involve extensive measurement or ‘mapping’ operations prior to the step of actually exposing or otherwise patterning the substrate at a target location. These operations, being time-consuming, limit the throughput of the lithography apparatus, and consequently increase the unit cost of the semiconductor or other products. Various steps have been taken to mitigate these delays in the prior art. For example, the introduction of dual wafer tables, so that two wafers can be loaded in the machine simultaneously. While a first wafer is undergoing exposure in an exposure station, a second wafer is undergoing measurement processes to establish an accurate ‘wafer grid’ and height map. The apparatus is designed so that the tables can be swapped without invalidating the measurement results, thereby reducing the overall cycle time per wafer. Other techniques to process measurement and exposure steps in parallel may be employed as well. Nevertheless, an overhead is still incurred which limits the throughput that can be achieved.
Additionally, because the measurement operations and the exposure operations for each wafer are somewhat separate in space and time, there is the potential for errors to creep in due to temperature fluctuations, mismatch between the dual stages and so forth. While these errors have been within tolerances for present generations, any source of error will become significant as one strives toward the goal of reaching ever-higher levels of resolution and overlay accuracy.